TSMC | The kingmaker of the AI era: Investment opportunities under the new compute hierarchy

• TSMC has become the “kingmaker” of the AI era: scarce leading-edge capacity is increasingly shaping industry competition.
• Profitability continues to strengthen: record margins reflect rising pricing power and operating leverage.
• The investment case is increasingly structural: TSMC is not just benefiting from AI, but helping determine the pace of its expansion.

We previously mentioned that TSMC had transitioned beyond a traditional foundry cycle into a structurally advantaged position within the global semiconductor supply chain. That thesis remains firmly intact — and is increasingly being reinforced by recent developments.

If anything, the latest 1Q26 results reinforce a more important evolution: TSMC is no longer merely a technology leader, but increasingly the central constraint in the global compute ecosystem. As AI demand accelerates and broadens across the stack, advanced-node capacity, rather than end-market demand, is becoming the defining factor of industry growth.

Margin Expansion Continues to Signal Structural Pricing Power

TSMC not only maintained a structurally high gross margin but also continued to expand it. Gross margin rose 3.9 percentage points quarter on quarter to 66.2%, supported by cost optimisation, productivity improvements, and higher capacity utilisation. Operating margin increased a further 4.1 percentage points to 58.1%, underscoring the strong operating leverage embedded in TSMC’s business model.

Table 1: 1Q26 Results Summary (USD)

Metric	Q1 2026	YoY	QoQ	vs Guidance
Revenue	35.9B	+40.6%	+6.4%	Above high-end
Gross Margin	66.2%	+7.4 pp	+3.9 pp	Above high-end
Operating Margin	58.1%	+9.6 pp	+4.1 pp	Above high-end
Net Income	18.1B	+58.3%	+13.2%	—
EPS per ADR	3.49	+58.3%	+13.2%	—

Source: TSMC and iFAST Compilation

Data as of 21 April 2026

More importantly, management indicated that N3 gross margin is expected to exceed the corporate average in 2H26 — a meaningful inflection point. Historically, leading-edge nodes tend to dilute margins during the ramp-up phase. The fact that N3 is now set to turn margin-accretive suggests a structurally tighter supply-demand balance at advanced nodes.

While the N2 ramp is expected to dilute gross margin by 2–3 percentage points in 2H26, management also guided for full-year 2026 dilution of only 2–3 percentage points, implying that the impact should remain manageable and is already largely anticipated by the market.

Graph 1: Gross Margin and Operating Margin of TSMC

AI Demand Continues to Reshape the Revenue Mix

Table 2: Net Revenue by Platform

Platform	1Q26 Mix	4Q25 Mix	QoQ Change
HPC	61%	55%	+20%
Smartphone	26%	32%	-11%
IoT	6%	5%	+12%
Automotive	4%	5%	-7%
DCE	1%	1%	+28%

Source: TSMC, iFAST Compilation

Data as of 21 April 2026

The revenue mix continues to tilt decisively toward High-Performance Computing (HPC), which now contributes a record 61% of total revenue. This underscores the sustained strength of AI-related demand, particularly across accelerators, CPUs, and custom silicon.

Importantly, the shift from generative AI to agentic AI is driving a step-change in compute intensity. As workloads become more complex and systems require far greater coordination, demand is broadening across the entire compute stack rather than remaining concentrated in GPUs alone.

Bottlenecks Are Expanding Across the AI Stack

A key feature of the current cycle is that supply constraints are no longer confined to GPUs.

As agentic AI gains traction, system architecture is undergoing a fundamental shift. CPUs are no longer peripheral components; they have become critical compute engines within AI systems, responsible for orchestration, task scheduling, and the efficient utilisation of GPU clusters. In many cases, CPU constraints are proving more binding than memory shortages. This highlights how bottlenecks are becoming increasingly system-wide across the compute stack.

This tightening is already evident in the recent extensions of lead times for leading-edge server CPUs, such as Intel Xeon and AMD EPYC. Industry checks suggest lead times for certain Intel server CPUs have stretched to as long as six months, while some AMD products have extended to 8–10 weeks or more. As a result, server CPU prices have risen by 10–20% in parts of the market.

At the same time, the role of the HBM base dies is evolving rapidly. These chips are incorporating greater functionality, higher compute density, and more advanced logic content, moving further away from traditional DRAM manufacturing processes. As a result, HBM4 and later generations are becoming increasingly dependent on leading-edge logic nodes and advanced packaging technologies such as CoWoS.

Related Article:

“Memory Supercycle: A Structural Shift Rewriting Supply and Demand Paradigm”

The implication is clear: supply constraints are no longer isolated to individual components. Instead, they are spreading across CPUs, GPUs, and memory — all converging on the same limited pool of advanced manufacturing capacity, an area where TSMC retains clear leadership. In this context, TSMC is not merely a beneficiary of the AI boom but one of its primary enablers.

TSMC as the Central Constraint and “Kingmaker”

TSMC has effectively become the “Kingmaker” of the AI era. In a market defined by constrained leading-edge capacity, competitive positioning is increasingly shaped not by demand alone, but by access to supply.

As shown in Table 3, most next-generation AI accelerators, including Nvidia, AMD, Google TPU, and AWS Trainium, are moving onto N3-class nodes. This migration is set to absorb a large share of leading-edge capacity through 2026–2027. AI-related demand is expected to account for around 60% of total N3 capacity in 2026. The imbalance is likely to worsen in 2027, with AI demand projected to rise to about 86% of total N3 wafer output.

Importantly, pressure on N3 capacity is not coming from AI alone. High-end consumer devices, including Apple’s M-series and A-series chips as well as Qualcomm’s flagship Snapdragon platforms, continue to rely on the same node, adding further strain to already tight supply.

Table 3：AI Accelerator Roadmap & Node Migration

Platform	2022	2023	2024	2025	2026
Nvidia	H100 (1x compute die, N4)	H200 (1x compute die, N4)	B200 / GB200 (2x compute die, N4P)	B300 / GB300 (2x compute die, N4P)	VR200 (2x compute die N3P; 2x I/O chiplet N3P)
AMD	—	—	MI300/325 (8x XCD N5; 4x AID N6)	MI350 (8x XCD N3; 2x AID N6)	MI400 (8x XCD N2; 2x AID N3P; 2x MID N3P)
TPU (AVGO)	TPU v4 (1x compute die, N7)	TPU v5e/v5p (1x compute die N5; 1x I/O chiplet N5)	TPU v6 (1x compute die N5P; 1x I/O chiplet N5P)	TPU v7 (2x compute die N3E; 1x I/O chiplet N3E)	TPU v8AX (2x compute die N3E; 1x I/O chiplet N3E)
TPU (MTK)	—	—	—	—	TPU v8X (1x compute die N3P; 1x I/O chiplet N3E)
Trainium	Trainium (1x compute die, N7)	—	Trainium2 (2x compute die, N5)	—	Trainium3 (2x compute die, N3P)
MTIA	—	—	MTIA Gen2 (1x compute die, N5)	MTIA Gen3 (1x compute die N3; 2x I/O chiplet N4)	MTIA Gen4 (2x compute die N3P; 2x I/O chiplet N3E)
MAIA	—	—	—	MAIA 200 (1x compute die, N3P)	—

Source: Semianalysis and iFAST Compilation

Date: 12 March 2026

As a result, TSMC is expanding 3nm capacity across multiple geographies — a clear departure from its historical practice of limiting capacity additions once a node had reached scale. This reflects management’s view that hyperscaler capital spending is unlikely to normalise anytime soon, and that leading-edge demand will remain structurally tight for several years.

Graph 2: 2026 CapEX Consensus of Hyperscalers was revised upward

Table 3: TSMC’s 3nm Global Expansion Plan

Site	Role	Volume Production	Technology
Tainan	New fab + conversion	1H27	N3
Arizona Fab 2	Second US fab	2H27	N3
Kumamoto Fab 2	Leading-edge upgrade	2028	N3

Source: TSMC, iFAST Compilation

Data as of 23 April 2026

Meanwhile, N2 has already entered volume production with encouraging initial yields. While the early ramp and overseas expansion are expected to introduce modest margin dilution, these are largely anticipated and reflect a deliberate trade-off to support long-term growth and capacity leadership.

Intangible Moat Remains Intact

TSMC’s competitive moat extends well beyond process technology, encompassing deep ecosystem integration and long-standing customer trust built over decades.

At the core of this moat is an exceptionally strong ecosystem lock-in. Leading customers have optimised their chip architectures, IP libraries, design flows, and EDA toolchains around TSMC’s Process Design Kits (PDKs) and Design-Technology Co-Optimization (DTCO) frameworks. Migrating a flagship design to an alternative foundry is therefore not incremental, but a fundamental redesign — requiring IP re-characterisation, EDA recalibration, full re-tapeouts, and a prolonged yield-learning cycle.

Industry estimates suggest such a transition would entail US$1.5–3 billion in direct engineering and qualification costs, alongside a 2–3 year delay and meaningful execution risk. This structural barrier explains why, despite incremental progress from competitors, leading AI and HPC customers — including Nvidia, AMD, Broadcom, Google, and Amazon Web Services — continue to allocate the vast majority of their advanced-node demand to TSMC.

Equally important — and often underappreciated — is the role of customer trust. Over more than three decades, TSMC has built a level of trust that effectively functions as an “intangible technology” in its own right. Jensen Huang has described this trust as one of TSMC’s most valuable assets, noting that despite decades of collaboration and hundreds of billions of dollars in business, NVIDIA and TSMC have rarely relied on formal contractual enforcement. His remark — “I trust them to put my company on top of them” — underscores the depth of this relationship.

In an industry where a single tape-out can cost over US$100 million and yield ramps can take years, such trust materially reduces perceived execution risk. It enables hyperscalers and fabless to commit to long-term roadmaps and concentrate on leading-edge demand with high conviction, even under conditions of extreme capacity tightness.

Technology Leadership: Reinforcing the Moat Through Next-Generation Innovations

TSMC continues to reinforce its technological leadership through ongoing innovation. The following are three key developments worth highlighting.

1.     Active Local Silicon Interconnect (aLSI) — The Next Evolution Beyond CoWoS-L

TSMC’s advanced packaging team has introduced Active Local Silicon Interconnect (aLSI), a significant upgrade over the passive silicon bridge used in CoWoS-L.

By embedding active transistors directly into the interposer bridge die, aLSI enhances signal integrity over longer distances while enabling a meaningful reduction in PHY circuitry on the main dies. This not only lowers power consumption but also frees up valuable silicon area for additional compute logic, HBM integration, or I/O expansion.

Table 5: aLSI vs. Traditional Solutions

Category	Traditional CoWoS-L / EMIB (Passive Bridge)	TSMC aLSI (Active Bridge)	Benefits for Next-Gen AI Accelerators
Bridge Type	Passive Metal Channel	Active Transistors + Edge-Triggered Transceiver (ETT)	Automatic signal shaping & amplification, significantly better signal integrity
PHY Circuit Requirements	Large and complex	Significantly reduced and simplified	Frees up valuable silicon area for compute / memory / I/O
Bump Pitch	45 µm	38.8 µm	Higher density, increased bandwidth
PHY Depth	1,043 µm	850 µm (≈19% reduction)	Recovers edge space for higher compute density
Signal Reach	Limited (signal easily degrades)	Maintains integrity over longer distances	Enables larger multi-die designs
Additional Features	None	Integrated eDTC (deep trench capacitors) for better power delivery	More stable power, less compromise on the power grid
Testing Stages	Simpler	Full KGD → KGS → KGP three-stage testing	Higher yield and reliability for volume production

Source: TSMC, iFAST Compilation

Data as of 23 April 2026

Overall, aLSI represents a natural evolution beyond CoWoS-L and is likely to become a key enabler for future large-scale AI accelerator designs, where interconnect efficiency and silicon utilisation are increasingly critical constraints.

2.     N16 STT-MRAM — Expanding into Automotive and Industrial eNVM

MRAM (Magnetic Random Access Memory) is a type of non-volatile memory that retains data even when power is off. It combines fast read/write speeds, low power consumption, and extremely high endurance, making it ideal for harsh environments such as automotive and industrial applications.

Compared to Samsung’s competing 8LPP eMRAM presented at the same conference, TSMC’s solution demonstrates superior performance and cost efficiency. This advancement allows TSMC to extend its technology leadership beyond traditional logic chips into specialty embedded non-volatile memory (eNVM), targeting the growing demand for reliable memory in automotive ADAS systems, zonal controllers, and over-the-air (OTA) firmware updates.

Graph 3：Innovation Design Features of TSMC N16 MRAM

Source: SemiAnalysis and iFast Compilations

Data as of 16 April 2026

3.     Co-Packaged Optics (CPO): Enabling Next-Generation AI Scale-Up and Scale-Out

As AI data centres evolve from scale-up architectures toward large-scale distributed systems, interconnect requirements are rising significantly. Traditional copper-based solutions face limitations in power efficiency, bandwidth density, and signal integrity over longer distances.

• Scale-up means making a single server or a single GPU cluster more powerful by adding more chips inside the same machine.
• Scale-out means connecting tens of thousands (or even hundreds of thousands) of GPUs across many machines to work together as one giant AI system.

Co-Packaged Optics (CPO) addresses these constraints by integrating optical engines directly with ASICs or GPUs within the same package, enabling higher bandwidth, lower latency, and improved energy efficiency — all critical for next-generation AI cluster scaling.

This extends TSMC’s leadership beyond advanced packaging into optical-electronic integration, reinforcing its role as a key enabler of next-generation AI infrastructure.

Guidance Points to Sustained Structural Growth

TSMC raised its full-year 2026 outlook, with revenue growth now expected to exceed 30% YoY and CapEx guided toward the high end of US$52–56B. Long-term gross margin targets were also reaffirmed at 56% or higher.

2Q26 guidance remains strong, with revenue expected at US$39.0–40.2B and gross margin in the range of 65.5–67.5%.

This combination of rising revenue, sustained margins, and elevated investment underscores the structural nature of the current cycle. Unlike previous upcycles, growth is being driven not only by demand expansion but also by persistent supply constraints at the leading edge.

Investment Implication

The key shift in this cycle is not the strength of AI demand, but the nature of the constraint.

The semiconductor industry is transitioning from a demand-driven cycle to a supply-constrained system, where access to advanced-node capacity determines growth. As bottlenecks expand across CPUs, GPUs, and memory, TSMC’s role evolves from a technology leader to the gatekeeper of compute supply.

TSMC is not simply a beneficiary of AI — it is the constraint through which the entire ecosystem must operate. In view of this, we have assigned a fair P/E multiple of 26x. This reflects our view that TSMC will maintain its dominant role in the AI era, serving as the industry’s kingmaker. On this basis, TSMC offers approximately 54% upside potential from current levels (as of 20 April 2025).

Table 4:  TSMC forecasted earnings and potential upside

TSM ADR	2025A	2026E	2027E	2028E
PE Ratio	34.4	25.6	20.2	16.9
Expected Earnings Growth	44.3%	34.5%	26.5%	19.9%
EPS (USD)	10.7	14.3	18.1	21.7
Target Price (USD)				565
Upside Potential (based on a fair PE ratio of 26x)				54%
Source: Bloomberg, iFAST Compilations.
Data as of 20 April 2026

Market/ Sector	ETF
Taiwan	Franklin FTSE Taiwan ETF (NYSE:FLTW)
Asia Semiconductor	Global X Asia Semiconductor ETF (HKEX:3119)